(ii) Plot Power and Area of the synthesized ALU as a function of clk period as you lower cycle time from 1.0ns to 0.1ns with the following cycle times until you see cycle time constraints violated:

1.0ns, 0.5ns, 0.4ns, 0.3ns, 0.275ns, 0.25ns, 0.225ns, 0.2ns,0.175ns, 0.15ns, 0.125ns, 0.1ns

report_qor will show how many paths failed to meet cycle time constraints.timing_report shows the gate and transition contributions to path delay for the most limiting path. power_report shows the distribution of power by component: Flip-Flop,logic gates, clock distribution

set_units -time ns

# Create a clock with T ns period and 50% duty cycle

create_clock -name clk -period 1.00 -waveform { 0 0.5 } [get_ports clk]

# ————————- Input constraints ——————-

set_input_delay 0.0150 -rise -clock clk [all_inputs]

# ————————- Output constraints ——————

set_output_delay 0.015 -rise -clock clk [all_outputs]

set_max_delay 1 -from [all_inputs] -to [all_outputs]

# Assume 50fF load capacitances everywhere:

set_load 0.050 [all_outputs]

# Set 10fF maximum capacitance on all inputs

set_max_capacitance 0.010 [all_inputs]

# set clock uncertainty of the system clock (skew and jitter)

set_clock_uncertainty -setup 0.005 [get_clocks clk]

set_clock_uncertainty -hold 0.005 [get_clocks clk]

# set maximum transition at output ports

set_max_transition 10 [current_design]

(iii) Modify the 8b ALU verilog module to synthesize each functional unit individually (8b adder, multiplier, divider etc) and repeat the task of scaling cycle time until you see a failing path [tool unable to synthesize unit using any of the knobs/options – VT, device width, fanout/fanin, etc]. Plot Power and Area as a function of cycle time for each of these functional units

(iv) Synthesis dependencies on cycle time constraint

Internal power is any power dissipated within the boundary of a cell = Cint * V*V *f + V * Isc

Short Circuit : = (V*ISC)