The Computer Systems Architecture laboratory exercise has two parts. In the first part you have written and validated a C program to simulate the operation of a direct mapped cache controller on an embedded processor. In the second part, you will use your simulator to analyse the impact of cache memory size and cache memory block size on the performance of the embedded system sorting an array of integer values using abubble sort algorithm.

You will work individually on this laboratory exercise; submitting a C program, a memory trace file used for validation and a short report.

2.   Embedded system memory architecture

The embedded processor is interfaced to a 256 Ki x 16-bit external data memory using a 20-bit address bus and a 16-bit data bus. The embedded processor contains a direct mapped cache controller for data accesses. The cache controller can be configured for cache sizes between 4 and 256 blocks and for cache block sizes between 2 and 32 16-bit words. The cache controller implements a Write-Allocate / Write-Back write policy.

3.   Bubble Sort Algorithm

You are provided with a memory trace file, bubble_sort_trace_nnn.txt, that contains the   values of the CPU address and data buses for each read and write access made by the CPU when sorting an array of random 16-bit integer values using a bubblesort algorithm.

Each student has their own unique trace file to analyse. You can find the value of the 3-digit ID number nnn identifying your unique trace file in the TRACE FILE ID column in Blackboard Gradebook.