The Computer Systems Architecture laboratory exercise has two parts. In the first part you will    write and validate a C program to simulate the operation of a direct mapped cache controller on an embedded processor. In the second part, you will use your simulator to analyse the impact of cache memory size and cache memory block size on the performance of the embedded system   when executing a sample program.

You will work individually on this laboratory exercise; submitting a C program, a memory trace file used for validation and a short report.

2.   Embedded system memory architecture

The embedded processor is interfaced to a 256 Ki x 16-bit external data memory using a 20-bit address bus and a 16-bit data bus. The embedded processor contains a direct mapped cache controller for data accesses. The cache controller can be configured for cache sizes between 4 and 256 blocks and for cache block sizes between 2 and 32 16-bit words. The cache controller implements a Write-Allocate / Write-Back write policy.